This invention relates generally to the field of semiconductor devices and, more specifically, to a method for manufacturing an asymmetric input/output (xe2x80x9cI/Oxe2x80x9d) transistor.
Semiconductor devices are used for many applications. One component used extensively in semiconductor devices is a transistor. There are many different types of transistors, including core transistors and input/output (xe2x80x9cI/Oxe2x80x9d) transistors. Typically, core transistors exist in a center region of a semiconductor chip while I/O transistors are dispersed around the perimeter of the chip. Additionally, core transistors usually run at a lower voltage than I/O transistors. The performance of I/O transistors is important for chip manufacturers to be competitive in the networking chip business (such as chips for routers).
According to one embodiment of the invention, a method of forming an asymmetric input/output (xe2x80x9cI/Oxe2x80x9d) transistor includes providing a semiconductor substrate having a core transistor region and an I/O transistor region, forming a first oxide layer outwardly from the semiconductor substrate, masking a first portion, less than a whole portion, of the I/O transistor region with a first photoresist layer, removing the first oxide layer from the core transistor region and a second portion of the I/O transistor region, removing the first photoresist layer, forming a second oxide layer outwardly from the substrate in the core transistor region and the second portion of the I/O transistor region and outwardly from the first oxide layer in the first portion of the I/O transistor region, forming a polysilicon layer outwardly from the second oxide layer, removing a portion of the polysilicon layer, the second oxide layer, and the third oxide layer to form gates for the core transistor region and the I/O transistor region, masking the first portion of the I/O transistor region with a second photoresist layer, doping a source region and a drain region of the core transistor region and a source region of the I/O transistor region with a first dopant, doping the source region and the drain region of the core transistor region and the source region of the I/O transistor region with a second dopant, removing the second photoresist layer, masking the core transistor region and the second portion of the I/O transistor region with a third photoresist layer, and doping a drain region of the I/O transistor region with a third dopant.
Embodiments of the invention provide a number of technical advantages. Embodiments of the invention may include all, some, or none of these advantages. For example, having an asymmetric input/output transistor may produce more drive current as well as improve the channel-hot carriers (xe2x80x9cCHCxe2x80x9d) lifetime because of the graded drain profile. In some embodiments, a chip designer may be able to tailor the off current, Ioff.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.